Octera IP/Reference Designs

IP – Reference Designs

4/7/2010

Type	Part Number	Description	Altera Devices Supported	Datasheet
Networking
IP	OCT-MDIO	Clause 22 target MDIO core	Cyclone 3 and above	Call for datasheet
IP	OCT-1588	Industrial Ethernet timestamping to the 1588 spec.	Cyclone 3 and above	Product Brief
IP	OCT-10GMAC OCT-10GHIGIG OCT-10GHIGIG+ OCT-10GHIGIG2	Fully customizable 10Gig MAC	Stratix 2 GX and above	Call for datasheet
IP	OCT-10GMACLITE	A small 10G MAC suitable for backplane type applications	Stratix 2 GX and above	Product Brief
IP	OC-FASTXAUI	A double- width (128-bit wide) XAUI PCS capable of running at bit rates higher than the Altera XAUI hard IP. Suitable for HiGig 2 and HiGig 2+.	Stratix 2 GX and above	Product Brief
IP	OCT-10GQUEUE	A queuing engine to allow multiple channels to be efficiently implemented in a 10G environment	Stratix 2 GX and above	Call for datasheet
Reference design	OCT-10GPKTPROCESSOR	A reference design using four soft core packet processing engines to process a 10G packet stream at line rate	Stratix 2 GX and above	Product Brief
Reference Design	OCT-10GBRIDGE	A complete SPI4 – XAUI bridge design using many Octera IP cores to provide queuing, arbitration, custom headers, tag insertion and other features	Stratix 2 GX and above	Call for datasheet
Computer / Embedded
IP	OCT-DDR3	A low speed DDR3 controller for cost sensitive applications	Cyclone 3	Product Brief
IP	OCT-SD/eMMC	Very small ‘streaming’ SD/eMMC interface for data logging type applications	Cyclone 3 and above	Call for datasheet
IP	OCT-I2C Master	I2C Master	Any	Call for datasheet
IP	OCT-I2C Slave	I2C Slave	Any	Call for datasheet
IP	OCT-405 PPC	Soft Core PPC Processor	Cyclone 3 and above	Call for datasheet
IP	OCT-AHB xxx	AHB Peripherals	Any	Call for datasheet
IP	OCT-JTAG TAP	JTAG TAPcontroller	Any	Call for datasheet
Reference design	OCT-NVDIMM	A complete design for moving data from DDR2/3 to flash memory at high speed for backup purposes	Cyclone 3 and above	Call for datasheet
Verification
Reference design	OCT-PCIeVER	An environment allowing easy verification and debug of PCIe in high performance systems	Stratix 2 and above	Product Brief
Reference design	OCT-VER	A complete verification environment for packet based systems allowing ‘C’ modeling, Ethernet traffic generation, early SW development and much more	Startix 2 and above	Product Brief
Reference design	OCT-TGEN	A stand alone Ethernet packet generator for use in verification and in HW. Allows scriptable Ethernet packets to be generated with specific traffic shapes	All – requires NIOS in HW	Call for datasheet